1. Field of the Invention
The invention generally relates to memory devices and, more particularly, to reducing current consumption during refresh operations.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices.
DRAM devices utilize memory cells (also referred to as storage nodes) consisting of one transistor and one capacitor. The cells are accessed by activating a wordline, switching on the respective transistors and coupling the respective capacitors to a bit line. The stored charge on the capacitor is then sensed by a sense amplifier coupled to the bit line to determine if a logical ‘1’ or ‘0’ bit of data is stored in the accessed cell.
Due to leakage current, charge stored in the capacitors may be lost to the point that the corresponding data is no longer valid. As a result, DRAM devices need refresh operations to maintain their stored data. Refresh operations are typically performed at regular time intervals by means of activating a word line, or a number of word lines, followed by a pre-charge of the same word line or word lines. This operation is repeated for the next word line or set of word lines until the whole chip is refreshed. Modern DRAM devices determine the word-line address for each refresh operation internally. Each refresh operation is initiated either externally, by means of an external command (e.g., a CAS before RAS or “CBR” refresh command) or internally when the device is in a “self refresh mode” or similar “standby”-like mode.
To optimize access to storage cells (e.g., to speed access, simplify signal routing, and/or facilitate layout), wordlines are segmented into groups of local wordlines or “wordline segments,” in which the collective segments are controlled by master wordlines. A master wordline and the local wordlines accessed by the master wordline may be referred to together as segmented wordlines. The local wordlines may be activated by activating the controlling master wordline for the group and asserting a signal on a control line for a local word line driver. In some cases, master wordlines and associated local wordlines may be further grouped into cell blocks which may be activated each time a master wordline and local wordline with a given cell block are accessed.
FIG. 1 is a timing diagram which depicts an exemplary timing of control signals applied during a self refresh mode to a memory device having cell blocks, master wordlines, and local wordlines. At time T0, the memory device may be operating in a normal mode wherein requested memory accesses (reads, writes, and refreshes) are being performed on the basis of an external clock signal, CLK. At time T1, the clock enable signal CKE may be lowered, thereby disabling the clock signal CLK. At time T2, a self refresh of the memory device may be initiated and the self refresh signal SREF may be asserted.
When the self refresh signal SREF is asserted, a timer, referred to as the self refresh timer (or self refresh oscillator) may begin generating a self refresh clock signal SREF_OSC which may be used to time row activations and precharges during the self refresh. Thus, at time T3, and continuing for the duration of the self refresh, SREF_OSC may be asserted periodically. The period of the SREF_OSC signal is referred to as the self refresh interval, tSRFI.
Each time SREF_OSC is asserted, a row address from a row address counter (RAC) may be used to select a cell block, a master wordline, and a local wordline for the row of memory cells to be refreshed. The high order bits of RAC may be used to select a cell block (indicated by the signal MUX), bits in the middle of RAC may be used to select a master wordline (indicated by Word Line <0:i+n>), and the lower order bits of RAC may be used to select a local wordline (indicated by MWLRST<0:3>). In the exemplary case depicted, there may be 16 cell blocks in a memory bank, 128 master wordlines in each cell block, and 4 local wordlines controlled by each master wordline. A signal (MDQS) used to connect local data lines to master data lines and secondary sense amplifiers in the memory device may also be asserted during each cycle.
When the self refresh begins at time T3, RAC may address 0, for example. Thus, the memory cells accessed using local wordline 0 and master wordline 0 in cell block 0 may be refreshed first. After each row of memory cells is refreshed, RAC may be incremented to access the next row. Thus, at time T4, the next local wordline (local wordline 1) and master wordline 0 in block 0 may be activated to perform a refresh of the associated memory cells. After local wordlines 0-3 controlled by master wordline 0 have been refreshed, the next master wordline (master wordline 1) and local wordline (local wordline 0) may be accessed to perform a refresh of the associated memory cells.
The refresh cycles for cell block 0 may be continued until the memory cells accessed by the local wordlines for the 128 master wordlines of the cell block 0 have been refreshed, at time T5. Thus, to refresh an entire cell block, 512 SREF_OSC cycles may be required (4 local wordlines*128 master wordlines=512). Then, beginning at time T6, the self refresh may continue with master wordline 0 and local wordline 0 in cell block 1 (as specified by the high order bits of RAC; again, indicated by the signal MUX). The self refresh may continue until time T8 when the cell blocks, master wordlines, local wordlines have been accessed and the associated memory cells have been refreshed. Thus, at time T8, the CKE signal may be asserted, enabling the clock signal CLK and at time T9 the self refresh signal SREF may be lowered, thereby terminating the self refresh.
For special-purpose low power DRAM devices, such as those utilized in cellular telephones and personal digital assistants (PDAs), it may be important to minimize current consumption, typically to increase battery life. As these devices often spend a large majority of their life in standby modes, requiring refresh to maintain their data (e.g., digital pictures, files, etc.), current consumption during refresh (referred to as IDD6 current) is particularly important. However, switching between local wordlines and between cell blocks as each memory cell is refreshed during self refresh operations of conventional DRAM devices typically results in additional current consumption.
For example, in some cases, a boosted voltage (e.g., a voltage boosted from a power supply voltage by a charge pump circuit, sometimes referred to as VPP) may be used during a self refresh for wordline and row control circuits. Where current is drawn from the VPP source, the memory device may consume additional power to boost VPP to an appropriate level. During self refresh, the current drawn from VPP may be increased due to frequent enabling and disabling of master and local wordlines, thereby increasing the power consumption of the memory device further.
Accordingly, what is needed are memory devices and methods which reduce the amount of current consumption during refresh operations.